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<div class="title">xgpiops_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gaff08ac5be0729f046324cae2706aaf9a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gaff08ac5be0729f046324cae2706aaf9a">XGpioPs_ReadReg</a>(BaseAddr,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddr) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:gaff08ac5be0729f046324cae2706aaf9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the given register.  <a href="group__gpiops__v3__1.html#gaff08ac5be0729f046324cae2706aaf9a">More...</a><br /></td></tr>
<tr class="separator:gaff08ac5be0729f046324cae2706aaf9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3ad586332c0958c5044450d735127337"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga3ad586332c0958c5044450d735127337">XGpioPs_WriteReg</a>(BaseAddr,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:ga3ad586332c0958c5044450d735127337"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes to the given register.  <a href="group__gpiops__v3__1.html#ga3ad586332c0958c5044450d735127337">More...</a><br /></td></tr>
<tr class="separator:ga3ad586332c0958c5044450d735127337"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register offsets for the GPIO. Each register is 32 bits.</div></td></tr>
<tr class="memitem:ga05aff41166bea96304f2fa71e21362c4"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_LSW_OFFSET</b>&#160;&#160;&#160;0x00000000U  /* Mask and Data Register LSW, WO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_MSW_OFFSET</b>&#160;&#160;&#160;0x00000004U  /* Mask and Data Register MSW, WO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_OFFSET</b>&#160;&#160;&#160;0x00000040U  /* Data Register, RW */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_RO_OFFSET</b>&#160;&#160;&#160;0x00000060U  /* Data Register - Input, RO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DIRM_OFFSET</b>&#160;&#160;&#160;0x00000204U  /* Direction Mode Register, RW */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_OUTEN_OFFSET</b>&#160;&#160;&#160;0x00000208U  /* Output Enable Register, RW */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTMASK_OFFSET</b>&#160;&#160;&#160;0x0000020CU  /* Interrupt Mask Register, RO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTEN_OFFSET</b>&#160;&#160;&#160;0x00000210U  /* Interrupt Enable Register, WO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTDIS_OFFSET</b>&#160;&#160;&#160;0x00000214U  /* Interrupt Disable Register, WO*/</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTSTS_OFFSET</b>&#160;&#160;&#160;0x00000218U  /* Interrupt Status Register, RO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_OFFSET</b>&#160;&#160;&#160;0x0000021CU  /* Interrupt Type Register, RW */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTPOL_OFFSET</b>&#160;&#160;&#160;0x00000220U  /* Interrupt Polarity Register, RW */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTANY_OFFSET</b>&#160;&#160;&#160;0x00000224U  /* Interrupt On Any Register, RW */</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Register offsets for each Bank.</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_MASK_OFFSET</b>&#160;&#160;&#160;0x00000008U  /* Data/Mask Registers offset */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_BANK_OFFSET</b>&#160;&#160;&#160;0x00000004U  /* Data Registers offset */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_REG_MASK_OFFSET</b>&#160;&#160;&#160;0x00000040U  /* Registers offset */</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt type reset values for each bank</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK0_RESET</b>&#160;&#160;&#160;0xFFFFFFFFU  /* Resets specific to Zynq */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK1_RESET</b>&#160;&#160;&#160;0x003FFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK2_RESET</b>&#160;&#160;&#160;0xFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK3_RESET</b>&#160;&#160;&#160;0xFFFFFFFFU  /* Reset common to both platforms */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK4_RESET</b>&#160;&#160;&#160;0xFFFFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK5_RESET</b>&#160;&#160;&#160;0xFFFFFFFFU</td></tr>
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